Senior FPGA Engineer
You will own programmable logic in the phased-array signal chain on modern AMD/Xilinx devices - designing and integrating high-rate datapaths between the board's custom silicon, configuring and debugging multi-gigabit transceiver links, and bringing your logic up on brand-new boards in the lab alongside the electrical engineering team. This is a hands-on design-and-hardware seat: your deliverables run on real boards headed for orbit, not in a simulation environment.
WHAT YOU'LL DO
- Design, integrate, and debug RTL for high-speed datapaths on AMD/Xilinx Versal and UltraScale+ devices.
- Configure and bring up high-speed transceivers (GTY-class) - link tuning, eye scans, and debug of live 25 Gbps-class serial links.
- Configure hardened Ethernet MAC IP (MRMAC/CMAC) for 25G/50G/100G traffic and validate high-rate links end to end.
- Build and maintain embedded Linux (PetaLinux/Yocto) images, device trees, and drivers for the FPGA processing system.
- Bring up your logic on first-article boards in the lab - JTAG, ILA, and bench instrumentation - working shoulder to shoulder with board design engineers.
- Build debug and monitoring hooks used across design validation campaigns.
REQUIRED EXPERIENCE
- 8+ years of RTL design (Verilog/SystemVerilog/VHDL) shipped in real products, with timing closure on modern devices.
- Hands-on high-speed serial experience: configuring and debugging multi-gigabit transceivers (GTY/GTM-class) and/or high-rate Ethernet (25G/50G/100G) on real hardware.
- Genuine board bring-up experience - debugging your own logic on new hardware at the bench, not only in simulation or emulation.
- U.S. citizenship or permanent residency (export-controlled program - required).
GCS is acting as an Employment Business in relation to this vacancy.
Senior FPGA Engineer
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