Senior FPGA Design Engineer
Job Title: Senior FPGA Design Engineer
About The Program:
Our client is building one of the world's largest low-Earth-orbit satellite constellations, delivering broadband internet from space. The hardware team behind it designs the electronics that drive the satellites' phased-array antennas: meter-scale, 20+ layer boards carrying custom silicon connected by ~25 Gbps high-speed serial links. Boards are designed, brought up, and validated in-house - engineers on this team see their own work running on real flight hardware.
The Role:
You will own programmable logic in the phased-array signal chain on AMD/Xilinx Versal devices - designing and integrating high-rate datapaths between the board's custom silicon, configuring and debugging multi-gigabit transceiver links, and bringing your logic up on brand-new boards in the lab alongside the electrical engineering team. This is a hands-on design-and-hardware seat: your deliverables run on real boards headed for orbit, not in a simulation environment.
What You'll Do:
Design, integrate, and debug RTL for high-speed datapaths on Versal ACAP devices.
Configure and bring up GTY transceivers - link tuning, eye scans, and debug of live 25 Gbps-class serial links.
Configure MRMAC hard IP for multi-rate Ethernet (25G / 50G / 100G) and validate high-rate traffic end to end.
Build and maintain embedded Linux (PetaLinux/Yocto) images, device trees, and drivers for the Versal processing system.
Bring up your logic on first-article boards in the lab - JTAG, ILA, and bench instrumentation - working shoulder to shoulder with board design engineers.
Build debug and monitoring hooks used across design validation campaigns.
Required Experience:
25G/50G/100G - Very high speed interfaces - hands-on design and bring-up at 25G / 50G / 100G.
MRMAC & GTY - Direct experience configuring MRMAC and GTY blocks - transceiver setup, tuning, and link debug on real hardware.
Versal ACAP - Working knowledge of the Versal ACAP architecture and toolchain (Vivado/Vitis).
Embedded Linux - Building images, device trees, and drivers for ARM-based FPGA processing systems (PetaLinux/Yocto).
8+ years of RTL design (Verilog/SystemVerilog/VHDL) shipped in real products, with timing closure on modern devices and genuine board bring-up experience.
Nice To Have:
JESD204, Aurora, or other high-speed converter/serial protocols.
Aerospace or high-reliability design exposure (DO-254, MIL-STD, radiation-aware design).
Prior satellite, SATCOM, radar, or high-speed networking product work.
Experience prototyping functions ahead of custom ASIC development.
GCS is acting as an Employment Business in relation to this vacancy.
Senior FPGA Design Engineer
Added 04/09/2026
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Added 06/08/2026
About the ProjectJoin an advanced satellite communications program focused on developing next-generation phased-array payload electronics for low Earth orbit (LEO) connectivity systems. This role supports the design and development of complex digital signal chain hardware that enables high-speed communication across satellite platforms.The FPGA Engineer will be responsible for designing and integrating programmable logic solutions that interface with custom silicon, beamforming devices, modems, and network processors. The position combines FPGA development with hands-on hardware integration and validation in a fast-paced engineering environment.Key ResponsibilitiesDesign, develop, and integrate FPGA-based solutions for phased-array communication systems.Create RTL for data movement, control, monitoring, and integration functions...
Added 06/08/2026
About the ProjectJoin an advanced satellite communications program focused on developing next-generation phased-array payload electronics for low Earth orbit (LEO) connectivity systems. This role supports the design and development of complex digital signal chain hardware that enables high-speed communication across satellite platforms.The FPGA Engineer will be responsible for designing and integrating programmable logic solutions that interface with custom silicon, beamforming devices, modems, and network processors. The position combines FPGA development with hands-on hardware integration and validation in a fast-paced engineering environment.Key ResponsibilitiesDesign, develop, and integrate FPGA-based solutions for phased-array communication systems.Create RTL for data movement, control, monitoring, and integration functions...
Added 06/08/2026
About the ProjectJoin an advanced satellite communications program focused on developing next-generation phased-array payload electronics for low Earth orbit (LEO) connectivity systems. This role supports the design and development of complex digital signal chain hardware that enables high-speed communication across satellite platforms.The FPGA Engineer will be responsible for designing and integrating programmable logic solutions that interface with custom silicon, beamforming devices, modems, and network processors. The position combines FPGA development with hands-on hardware integration and validation in a fast-paced engineering environment.Key ResponsibilitiesDesign, develop, and integrate FPGA-based solutions for phased-array communication systems.Create RTL for data movement, control, monitoring, and integration functions...
Added 06/08/2026
About the ProjectJoin an advanced satellite communications program focused on developing next-generation phased-array payload electronics for low Earth orbit (LEO) connectivity systems. This role supports the design and development of complex digital signal chain hardware that enables high-speed communication across satellite platforms.The FPGA Engineer will be responsible for designing and integrating programmable logic solutions that interface with custom silicon, beamforming devices, modems, and network processors. The position combines FPGA development with hands-on hardware integration and validation in a fast-paced engineering environment.Key ResponsibilitiesDesign, develop, and integrate FPGA-based solutions for phased-array communication systems.Create RTL for data movement, control, monitoring, and integration functions...
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