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We are seeking a highly experienced Senior FPGA Engineer to support the development of advanced satellite communications payload hardware.

This role focuses on developing FPGA logic for advanced phased-array payload systems. The ideal candidate will have strong expertise in RTL design, high-speed interfaces, timing closure, and hands-on hardware bring-up and debugging.

This is a highly hands-on engineering position requiring experience taking FPGA designs from RTL development through hardware validation. The engineer will work closely with electrical, hardware, board design, and systems engineering teams in a laboratory environment.

What You'll DoDesign, develop, and implement FPGA RTL using Verilog, SystemVerilog, or VHDL.Develop and integrate high-speed interfaces and protocols, including JESD204, Aurora, PCIe, and Ethernet.Own timing closure, timing constraints, clocking architecture, and FPGA performance optimization.Perform FPGA bring-up and debug on new hardware platforms using JTAG, ILA, ChipScope, SignalTap, and laboratory equipment.Develop FPGA logic for high-speed data movement, control, and communication between custom silicon devices.Prototype and validate new functionality ahead of next-generation ASIC development.Collaborate with board design, hardware validation, and systems engineering teams.Troubleshoot complex FPGA and hardware integration issues and drive designs through successful validation.What We're Looking For8+ years of FPGA/RTL design and development experience.Strong proficiency in Verilog, SystemVerilog, or VHDL.Hands-on experience with high-speed FPGA transceivers and serial communication protocols.Proven experience achieving timing closure on complex FPGA designs.Strong board bring-up, hardware debugging, and lab validation experience.Experience working with AMD/Xilinx or Intel/Altera FPGA platforms.Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical field.Nice to HaveExperience with JESD204, DSP, FFT, beamforming, SDR, radar, or wireless communication systems.Aerospace, satellite communications, or space-based hardware experience.Experience with Zynq, Versal, UVM, Tcl, or Python.Knowledge of radiation-tolerant FPGA design techniques, including Triple Modular Redundancy (TMR) and configuration scrubbing.Why This Role?

This is an opportunity to contribute to cutting-edge satellite communications technology and develop FPGA solutions for advanced space-based hardware systems.

You will work alongside experienced hardware and systems engineering teams, solve challenging engineering problems, and take ownership of FPGA designs from initial RTL development through real-world hardware validation and deployment.

GCS is acting as an Employment Business in relation to this vacancy.

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Senior FPGA Design EngineerAbout the Opportunity

Our client is building one of the world's largest low-Earth-orbit (LEO) satellite constellations, delivering broadband internet from space. With hundreds of satellites already in orbit and thousands more planned, they are developing the next generation of space-based communications technology.

The hardware team designs the advanced electronics powering phased-array antennas, including complex multi-layer boards, custom silicon, and high-speed serial interfaces. Engineers on this team have the unique opportunity to see their designs deployed on satellites operating in orbit.

What You'll DoDesign, integrate, and debug RTL on AMD/Xilinx Versal and UltraScale+ FPGAs.Configure and bring up GTY-class transceivers and debug 25 Gbps+ serial links.Implement and validate high-speed Ethernet solutions using MRMAC/CMAC IP (25G/50G/100G).Develop and maintain embedded Linux environments using PetaLinux/Yocto.Perform FPGA and board bring-up using JTAG, ILA, and lab test equipment.Work closely with hardware engineers to support system validation and debugging.Create diagnostic and monitoring tools to support development and test activities.Required Qualifications8+ years of FPGA/RTL development experience using Verilog, SystemVerilog, or VHDL.Hands-on experience with high-speed serial transceivers (GTY/GTM) and/or 25G/50G/100G Ethernet.Proven board bring-up and hardware debugging experience.Experience achieving timing closure on modern FPGA devices.U.S. Citizenship or Permanent Residency required.Preferred QualificationsExperience with AMD/Xilinx Versal ACAP and UltraScale+ platforms.MRMAC or CMAC configuration and optimization experience.Strong background in PetaLinux, Yocto, device trees, and embedded Linux drivers.Nice to HaveExperience with JESD204, Aurora, or similar high-speed protocols.Aerospace, satellite communications, radar, or networking experience.Familiarity with high-reliability or radiation-aware designs.FPGA prototyping experience supporting ASIC development.

Why Join?
Work on cutting-edge satellite technology, collaborate with top-tier engineering teams, and see your FPGA designs deployed on real hardware headed for orbit.

GCS is acting as an Employment Business in relation to this vacancy.

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Senior FPGA Engineer About the Opportunity

Our client is building one of the world's largest low-Earth-orbit (LEO) satellite constellations, delivering broadband internet from space. With hundreds of satellites already in orbit and thousands more planned, they are developing the next generation of space-based communications technology.

The hardware team designs the advanced electronics powering phased-array antennas, including complex multi-layer boards, custom silicon, and high-speed serial interfaces. Engineers on this team have the unique opportunity to see their designs deployed on satellites operating in orbit.

What You'll DoDesign, integrate, and debug RTL on AMD/Xilinx Versal and UltraScale+ FPGAs.Configure and bring up GTY-class transceivers and debug 25 Gbps+ serial links.Implement and validate high-speed Ethernet solutions using MRMAC/CMAC IP (25G/50G/100G).Develop and maintain embedded Linux environments using PetaLinux/Yocto.Perform FPGA and board bring-up using JTAG, ILA, and lab test equipment.Work closely with hardware engineers to support system validation and debugging.Create diagnostic and monitoring tools to support development and test activities.Required Qualifications8+ years of FPGA/RTL development experience using Verilog, SystemVerilog, or VHDL.Hands-on experience with high-speed serial transceivers (GTY/GTM) and/or 25G/50G/100G Ethernet.Proven board bring-up and hardware debugging experience.Experience achieving timing closure on modern FPGA devices.U.S. Citizenship or Permanent Residency required.Preferred QualificationsExperience with AMD/Xilinx Versal ACAP and UltraScale+ platforms.MRMAC or CMAC configuration and optimization experience.Strong background in PetaLinux, Yocto, device trees, and embedded Linux drivers.Nice to HaveExperience with JESD204, Aurora, or similar high-speed protocols.Aerospace, satellite communications, radar, or networking experience.Familiarity with high-reliability or radiation-aware designs.FPGA prototyping experience supporting ASIC development.

Why Join?
Work on cutting-edge satellite technology, collaborate with top-tier engineering teams, and see your FPGA designs deployed on real hardware headed for orbit.

GCS is acting as an Employment Business in relation to this vacancy.

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You will own programmable logic in the phased-array signal chain on modern AMD/Xilinx devices - designing and integrating high-rate datapaths between the board's custom silicon, configuring and debugging multi-gigabit transceiver links, and bringing your logic up on brand-new boards in the lab alongside the electrical engineering team. This is a hands-on design-and-hardware seat: your deliverables run on real boards headed for orbit, not in a simulation environment.

WHAT YOU'LL DO

Design, integrate, and debug RTL for high-speed datapaths on AMD/Xilinx Versal and UltraScale+ devices. Configure and bring up high-speed transceivers (GTY-class) - link tuning, eye scans, and debug of live 25 Gbps-class serial links. Configure hardened Ethernet MAC IP (MRMAC/CMAC) for 25G/50G/100G traffic and validate high-rate links end to end. Build and maintain embedded Linux (PetaLinux/Yocto) images, device trees, and drivers for the FPGA processing system. Bring up your logic on first-article boards in the lab - JTAG, ILA, and bench instrumentation - working shoulder to shoulder with board design engineers. Build debug and monitoring hooks used across design validation campaigns.

REQUIRED EXPERIENCE

8+ years of RTL design (Verilog/SystemVerilog/VHDL) shipped in real products, with timing closure on modern devices. Hands-on high-speed serial experience: configuring and debugging multi-gigabit transceivers (GTY/GTM-class) and/or high-rate Ethernet (25G/50G/100G) on real hardware. Genuine board bring-up experience - debugging your own logic on new hardware at the bench, not only in simulation or emulation. U.S. citizenship or permanent residency (export-controlled program - required).

GCS is acting as an Employment Business in relation to this vacancy.

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Job Title: Senior FPGA Design Engineer

About The Program:

Our client is building one of the world's largest low-Earth-orbit satellite constellations, delivering broadband internet from space. The hardware team behind it designs the electronics that drive the satellites' phased-array antennas: meter-scale, 20+ layer boards carrying custom silicon connected by ~25 Gbps high-speed serial links. Boards are designed, brought up, and validated in-house - engineers on this team see their own work running on real flight hardware.

The Role:

You will own programmable logic in the phased-array signal chain on AMD/Xilinx Versal devices - designing and integrating high-rate datapaths between the board's custom silicon, configuring and debugging multi-gigabit transceiver links, and bringing your logic up on brand-new boards in the lab alongside the electrical engineering team. This is a hands-on design-and-hardware seat: your deliverables run on real boards headed for orbit, not in a simulation environment.

What You'll Do:

Design, integrate, and debug RTL for high-speed datapaths on Versal ACAP devices.

Configure and bring up GTY transceivers - link tuning, eye scans, and debug of live 25 Gbps-class serial links.

Configure MRMAC hard IP for multi-rate Ethernet (25G / 50G / 100G) and validate high-rate traffic end to end.

Build and maintain embedded Linux (PetaLinux/Yocto) images, device trees, and drivers for the Versal processing system.

Bring up your logic on first-article boards in the lab - JTAG, ILA, and bench instrumentation - working shoulder to shoulder with board design engineers.

Build debug and monitoring hooks used across design validation campaigns.

Required Experience:

25G/50G/100G - Very high speed interfaces - hands-on design and bring-up at 25G / 50G / 100G.

MRMAC & GTY - Direct experience configuring MRMAC and GTY blocks - transceiver setup, tuning, and link debug on real hardware.

Versal ACAP - Working knowledge of the Versal ACAP architecture and toolchain (Vivado/Vitis).

Embedded Linux - Building images, device trees, and drivers for ARM-based FPGA processing systems (PetaLinux/Yocto).

8+ years of RTL design (Verilog/SystemVerilog/VHDL) shipped in real products, with timing closure on modern devices and genuine board bring-up experience.

Nice To Have:

JESD204, Aurora, or other high-speed converter/serial protocols.

Aerospace or high-reliability design exposure (DO-254, MIL-STD, radiation-aware design).

Prior satellite, SATCOM, radar, or high-speed networking product work.

Experience prototyping functions ahead of custom ASIC development.

GCS is acting as an Employment Business in relation to this vacancy.

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Senior FPGA Design Engineer About the Opportunity

Our client is building one of the world's largest low-Earth-orbit (LEO) satellite constellations, delivering broadband internet from space. With hundreds of satellites already in orbit and thousands more planned, they are developing the next generation of space-based communications technology.

The hardware team designs the advanced electronics powering phased-array antennas, including complex multi-layer boards, custom silicon, and high-speed serial interfaces. Engineers on this team have the unique opportunity to see their designs deployed on satellites operating in orbit.

What You'll DoDesign, integrate, and debug RTL on AMD/Xilinx Versal and UltraScale+ FPGAs.Configure and bring up GTY-class transceivers and debug 25 Gbps+ serial links.Implement and validate high-speed Ethernet solutions using MRMAC/CMAC IP (25G/50G/100G).Develop and maintain embedded Linux environments using PetaLinux/Yocto.Perform FPGA and board bring-up using JTAG, ILA, and lab test equipment.Work closely with hardware engineers to support system validation and debugging.Create diagnostic and monitoring tools to support development and test activities.Required Qualifications8+ years of FPGA/RTL development experience using Verilog, SystemVerilog, or VHDL.Hands-on experience with high-speed serial transceivers (GTY/GTM) and/or 25G/50G/100G Ethernet.Proven board bring-up and hardware debugging experience.Experience achieving timing closure on modern FPGA devices.U.S. Citizenship or Permanent Residency required.Preferred QualificationsExperience with AMD/Xilinx Versal ACAP and UltraScale+ platforms.MRMAC or CMAC configuration and optimization experience.Strong background in PetaLinux, Yocto, device trees, and embedded Linux drivers.Nice to HaveExperience with JESD204, Aurora, or similar high-speed protocols.Aerospace, satellite communications, radar, or networking experience.Familiarity with high-reliability or radiation-aware designs.FPGA prototyping experience supporting ASIC development.

Why Join?
Work on cutting-edge satellite technology, collaborate with top-tier engineering teams, and see your FPGA designs deployed on real hardware headed for orbit.

GCS is acting as an Employment Business in relation to this vacancy.

Read less

Senior FPGA Engineer About the Opportunity

Our client is building one of the world's largest low-Earth-orbit (LEO) satellite constellations, delivering broadband internet from space. With hundreds of satellites already in orbit and thousands more planned, they are developing the next generation of space-based communications technology.

The hardware team designs the advanced electronics powering phased-array antennas, including complex multi-layer boards, custom silicon, and high-speed serial interfaces. Engineers on this team have the unique opportunity to see their designs deployed on satellites operating in orbit.

What You'll DoDesign, integrate, and debug RTL on AMD/Xilinx Versal and UltraScale+ FPGAs.Configure and bring up GTY-class transceivers and debug 25 Gbps+ serial links.Implement and validate high-speed Ethernet solutions using MRMAC/CMAC IP (25G/50G/100G).Develop and maintain embedded Linux environments using PetaLinux/Yocto.Perform FPGA and board bring-up using JTAG, ILA, and lab test equipment.Work closely with hardware engineers to support system validation and debugging.Create diagnostic and monitoring tools to support development and test activities.Required Qualifications8+ years of FPGA/RTL development experience using Verilog, SystemVerilog, or VHDL.Hands-on experience with high-speed serial transceivers (GTY/GTM) and/or 25G/50G/100G Ethernet.Proven board bring-up and hardware debugging experience.Experience achieving timing closure on modern FPGA devices.U.S. Citizenship or Permanent Residency required.Preferred QualificationsExperience with AMD/Xilinx Versal ACAP and UltraScale+ platforms.MRMAC or CMAC configuration and optimization experience.Strong background in PetaLinux, Yocto, device trees, and embedded Linux drivers.Nice to HaveExperience with JESD204, Aurora, or similar high-speed protocols.Aerospace, satellite communications, radar, or networking experience.Familiarity with high-reliability or radiation-aware designs.FPGA prototyping experience supporting ASIC development.

Why Join?
Work on cutting-edge satellite technology, collaborate with top-tier engineering teams, and see your FPGA designs deployed on real hardware headed for orbit.

GCS is acting as an Employment Business in relation to this vacancy.

Read less

FPGA Engineer About the Opportunity

Our client is building one of the world's largest low-Earth-orbit (LEO) satellite constellations, delivering broadband internet from space. With hundreds of satellites already in orbit and thousands more planned, they are developing the next generation of space-based communications technology.

The hardware team designs the advanced electronics powering phased-array antennas, including complex multi-layer boards, custom silicon, and high-speed serial interfaces. Engineers on this team have the unique opportunity to see their designs deployed on satellites operating in orbit.

What You'll DoDesign, integrate, and debug RTL on AMD/Xilinx Versal and UltraScale+ FPGAs.Configure and bring up GTY-class transceivers and debug 25 Gbps+ serial links.Implement and validate high-speed Ethernet solutions using MRMAC/CMAC IP (25G/50G/100G).Develop and maintain embedded Linux environments using PetaLinux/Yocto.Perform FPGA and board bring-up using JTAG, ILA, and lab test equipment.Work closely with hardware engineers to support system validation and debugging.Create diagnostic and monitoring tools to support development and test activities.Required Qualifications8+ years of FPGA/RTL development experience using Verilog, SystemVerilog, or VHDL.Hands-on experience with high-speed serial transceivers (GTY/GTM) and/or 25G/50G/100G Ethernet.Proven board bring-up and hardware debugging experience.Experience achieving timing closure on modern FPGA devices.U.S. Citizenship or Permanent Residency required.Preferred QualificationsExperience with AMD/Xilinx Versal ACAP and UltraScale+ platforms.MRMAC or CMAC configuration and optimization experience.Strong background in PetaLinux, Yocto, device trees, and embedded Linux drivers.Nice to HaveExperience with JESD204, Aurora, or similar high-speed protocols.Aerospace, satellite communications, radar, or networking experience.Familiarity with high-reliability or radiation-aware designs.FPGA prototyping experience supporting ASIC development.

Why Join?
Work on cutting-edge satellite technology, collaborate with top-tier engineering teams, and see your FPGA designs deployed on real hardware headed for orbit.

GCS is acting as an Employment Business in relation to this vacancy.

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Job Title: FPGA Engineer

About the Role:

We are seeking an experienced FPGA Engineer to design and develop advanced FPGA solutions for a next-generation satellite communication system. This is a unique opportunity to contribute to the development of cutting-edge networking technology with minimal legacy constraints. You will work closely with system architects and cross-functional engineering teams to define, implement, validate, and release FPGA-based solutions supporting high-performance communication systems.

Key Responsibilities:

Own the development and delivery of one or more FPGA bitstreams.

Design, develop, and implement complex FPGA architectures using Verilog HDL.

Lead FPGA development across the complete lifecycle, including:

Microarchitecture

RTL Design

Physical Implementation

Timing Closure

Simulation & Verification

Lab Validation

Production Release

Develop FPGA-based networking and digital communication functions.

Collaborate with system architects, hardware engineers, firmware, and software teams to implement and validate FPGA solutions.

Build FPGA prototypes to evaluate architecture and design tradeoffs.

Support hardware bring-up, system integration, and debugging involving FPGA, RF, firmware, and networking components.

Perform synthesis, place & route, timing analysis, and design optimization.

Develop comprehensive testbenches and simulation environments.

Debug FPGA designs in both simulation and hardware environments.

Drive design tradeoff analysis focused on performance, power, cost, area, and customer experience.

Create technical documentation including design specifications, verification plans, and test documentation.

Support manufacturing, production deployment, and post-release engineering activities.

Required Qualifications:

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field.

7+ years of hands-on FPGA design experience.

Strong expertise with Verilog HDL for RTL design and verification.

Experience designing with AMD Xilinx Versal ACAP FPGA architecture.

Experience working with Microchip IGLOO2 FPGA platforms.

Proficiency with FPGA development tools such as:

Xilinx Vivado

Microchip Libero SoC

Strong understanding of:

Digital logic design

Timing analysis and timing closure

Clock Domain Crossing (CDC)

Experience with simulation tools such as:

ModelSim

Vivado Simulator

VCS (or equivalent)

Experience using scripting languages such as Python, TCL, or Perl for design automation.

Strong debugging, analytical, and problem-solving skills.

Understanding of industry-standard communication protocols.

Preferred Qualifications:

Experience with SystemVerilog and UVM verification methodologies.

Experience with high-speed interfaces including:

PCIe

DDR

Ethernet

SerDes

Familiarity with embedded systems and hardware/software integration.

Experience using version control systems such as Git or SVN.

Background in digital communications, networking, or signal processing.

Experience working with DO-254 or other safety-critical design standards.

Required Technical Skills:

HDL Languages: Verilog (required), SystemVerilog (preferred)

FPGA Platforms: AMD Xilinx Versal ACAP, Microchip IGLOO2

Design Tools: Vivado, Libero SoC

Simulation: ModelSim, Vivado Simulator, VCS (or equivalent)

Scripting: Python, TCL, Perl

Version Control: Git, SVN

Protocols: Industry-standard communication protocols

Design Expertise: RTL Design, FPGA Verification, Timing Closure, CDC Analysis, Physical Implementation, Hardware Bring-up

GCS is acting as an Employment Business in relation to this vacancy.

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Job Title: FPGA Engineer

About the Role:

We are seeking an experienced FPGA Engineer to design and develop advanced FPGA solutions for a next-generation satellite communication system. This is a unique opportunity to contribute to the development of cutting-edge networking technology with minimal legacy constraints. You will work closely with system architects and cross-functional engineering teams to define, implement, validate, and release FPGA-based solutions supporting high-performance communication systems.

Key Responsibilities:

Own the development and delivery of one or more FPGA bitstreams.

Design, develop, and implement complex FPGA architectures using Verilog HDL.

Lead FPGA development across the complete lifecycle, including:

Microarchitecture

RTL Design

Physical Implementation

Timing Closure

Simulation & Verification

Lab Validation

Production Release

Develop FPGA-based networking and digital communication functions.

Collaborate with system architects, hardware engineers, firmware, and software teams to implement and validate FPGA solutions.

Build FPGA prototypes to evaluate architecture and design tradeoffs.

Support hardware bring-up, system integration, and debugging involving FPGA, RF, firmware, and networking components.

Perform synthesis, place & route, timing analysis, and design optimization.

Develop comprehensive testbenches and simulation environments.

Debug FPGA designs in both simulation and hardware environments.

Drive design tradeoff analysis focused on performance, power, cost, area, and customer experience.

Create technical documentation including design specifications, verification plans, and test documentation.

Support manufacturing, production deployment, and post-release engineering activities.

Required Qualifications:

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field.

7+ years of hands-on FPGA design experience.

Strong expertise with Verilog HDL for RTL design and verification.

Experience designing with AMD Xilinx Versal ACAP FPGA architecture.

Experience working with Microchip IGLOO2 FPGA platforms.

Proficiency with FPGA development tools such as:

Xilinx Vivado

Microchip Libero SoC

Strong understanding of:

Digital logic design

Timing analysis and timing closure

Clock Domain Crossing (CDC)

Experience with simulation tools such as:

ModelSim

Vivado Simulator

VCS (or equivalent)

Experience using scripting languages such as Python, TCL, or Perl for design automation.

Strong debugging, analytical, and problem-solving skills.

Understanding of industry-standard communication protocols.

Preferred Qualifications:

Experience with SystemVerilog and UVM verification methodologies.

Experience with high-speed interfaces including:

PCIe

DDR

Ethernet

SerDes

Familiarity with embedded systems and hardware/software integration.

Experience using version control systems such as Git or SVN.

Background in digital communications, networking, or signal processing.

Experience working with DO-254 or other safety-critical design standards.

Required Technical Skills:

HDL Languages: Verilog (required), SystemVerilog (preferred)

FPGA Platforms: AMD Xilinx Versal ACAP, Microchip IGLOO2

Design Tools: Vivado, Libero SoC

Simulation: ModelSim, Vivado Simulator, VCS (or equivalent)

Scripting: Python, TCL, Perl

Version Control: Git, SVN

Protocols: Industry-standard communication protocols

Design Expertise: RTL Design, FPGA Verification, Timing Closure, CDC Analysis, Physical Implementation, Hardware Bring-up

GCS is acting as an Employment Business in relation to this vacancy.

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